Staff Physical Design Engineer

Your Role in Our Mission:

At Normal Computing, we're developing a new thermodynamic computing paradigm to accelerate probabilistic AI workloads by embracing noise, rather than fighting it. Our work combines foundational research on the physics of computing with a mission to ship scalable, reliable silicon and systems to revolutionize AI.

As a physical design engineer at Normal, you will work closely with the silicon and hardware R&D team to develop and implement novel thermodynamic computing architectures. You will have significant ownership of chip floorplanning, top-level integration, and signoff, with the goal of delivering reliable silicon and achieving first-silicon-success.

Responsibilities:

1. You will play a key role in the entire development process of our silicon, from idea to architecture to implementation to tape-out.
2. Contribute new ideas for potential thermodynamic computing technologies and architectures.
3. Floorplan a complex mixed-signal chip with analog, digital, and mixed-signal blocks.
4. Drive requirements for and support analog layouts.
5. Lead physical implementation of digital and mixed-signal chips using Cadence tools.
6. Perform top-level chip signoff, including timing checks, power analysis, logical equivalence checking, EM/IR analysis, and design rule checking.
7. Participate in the tape-out, bring-up, and testing of Normal's silicon.

What Makes You A Great Fit:

1. Strong familiarity with analog-on-top and digital-on-top design flows for mixed-signal chips.
2. Proficiency with the Cadence suite of physical design tools, including Virtuoso, Genus, Innovus, Quartus, Tempus and Voltus.
3. Proficiency generating LEF and Liberty files using Cadence Liberate and Cadence Abstract Generator.
4. Fluency in Verilog and/or SystemVerilog.
5. Experience in scripting languages, including Python, Perl, and/or TCL.
6. Excellent communication skills and the ability to work well on a small, interdisciplinary team.

Bonus Points For:

1. Experience mentoring or managing junior engineers.
2. Experience with asynchronous logic.
3. Experience with mixed-signal PLL design.
4. Experience with foundries & foundry aggregators to help acquire, set up, and support PDKs, set up and perform LVS and DRC flows, and tape out a completed silicon product.
5. Experience selecting, sourcing, and integrating third-party IP from multiple different vendors into a silicon product.
6. Familiarity with the wafer test, packaging, and chip testing process, including creating package drawings, writing test plans, and working with an external testing provider to implement testing at scale.
7. Experience working at a startup.